Recently, semiconductor memory devices increase steadily both in their integration degree and capacity. Research has been conducted for miniaturization of memory cells in a MOS dynamic RAM (DRAM) comprising a single MOSFET and a single MOS capacitor.
Due to the miniaturization of the memory cells, however, the area of the capacitor for storing information (electric charges) is reduced. As a result, soft errors such as misreading of the contents of the memory device or breakage of the contents of the memory device by .alpha.-rays have become problems to be solved.
Various methods have been proposed to increase integration degree and capacity while preventing the soft errors. In the methods, efforts have been made to substantially increase the capacity of the capacitor and hence stored electric charge without increasing the area occupied by the capacitor.
One proposal is a DRAM having the following trench type capacitor structure.
A plan view and a cross-sectional view of such DRAM is shown in FIGS. 13(a) and 13(b). in which the DRAM comprises trenches 3 (3.sub.1, 3.sub.2, . . . ) formed in a surface of a p-type silicon substrate 1 and n-type layers 6 (6.sub.1, 6.sub.2, . . . ) formed on the inner walls of the trenches 3, capacitor insulator films 9 and plate electrodes 10 embedded in this order on the surfaces of the n-type layers to form capacitors. With this structure, the area (capacity) of the capacitor is increased without increasing the size of the capacitor.
Each MOSFET comprises source and drain regions 14 of an n-type layer and a gate electrode 13 (13.sub.1, 13.sub.2, . . . ), a gate insulator film 12 being formed between the source and drain regions 14 and the gate electrode 13, and formed within an element region defined by a yield oxide film 2 which is formed on the surface of the silicon substrate 1. Each MOS capacitor comprises an n-type layer 6 disposed on the inner wall of an adjacent trench 3 and connected to the n-type layer source or drain region 14 (14.sub.1, 14.sub.2, . . . ), a capacitor insulator film 9 formed on the surface of the n-type layer 6 and a plate electrode 10 embedded in the trench 3.
In this structure, the inner wall of the trench 3 is used to form the MOS capacitor. Therefore, the capacity of the capacitor is increased several times as large as that of a planar structure. Thus, this structure prevents a decrease in the electric charges stored in the memory cell even if the area occupied by the memory cell is reduced. Accordingly, this structure provides a small-sized DRAM having a large capacity of memory.
With the above-described structure, however, as the distance between the trenches 3.sub.1 and 3.sub.2 of adjacent memory cells is reduced, stored electric charges (information) are likely to be lost by punch-through which causes an error in the stored data.
This error occurs in a situation where information charges are stored in the n-type layer 6.sub.1 of one trench 3.sub.1 and no information charges are stored in the n-type layer 6.sub.2 of the other trench 3.sub.2. In such situation, the information charges stored in the n-type layer 6.sub.1 move to the other n-type layer 6.sub.2. As the depth of the trench increases, an error is more likely to occur. This is because, the length for the horizontal diffusion in the n-type layer 6 increases as the trench becomes deeper, so that the distance between adjacent n-type layers becomes relatively reduced.
Therefore, if a trench is, for example, 5 um deep, it is very difficult to reduce the distance between the adjacent trenches to 1.5 .mu.m or less.
This has become a big problem which prevents a further increase in the integration degree of DRAMs.
Referring to FIG. 14, a structure is proposed in order to solve the above problem in the structure, a capacitor is formed by sequentially forming a storage node electrode 7, a capacitor insulator film 9 and a plate electrode 10 through an insulator film 4 (4.sub.1, 4.sub.2, 4.sub.3) on the inner wall of a trench 3 (3.sub.1, 3.sub.2, 3.sub.3)(Refer to Unexamined Japanese Patent Publication Sho 61-67954). The numeral 6s denotes an n-type layer which connects the storage node electrode 7 to an n-type layer 14 which constitutes the source and drain regions, and 17 and 18 denote a bit line and a protective film, respectively.
Since the trench inside wall is covered with the insulator film 4 in this structure, there is no danger of leakage due to punch-through which would otherwise occur between the n-type layers 6.sub.1 and 6.sub.2 in the structure of FIG. 13 even if the distance between the adjacent trenches is reduced.
However, there is a problem of reduction in the S/N ratio due to many depletion layers present in the interface between the substrate 1 and insulator film 4. These depletion layers are a depletion layer extending from the n-type layer 14 constituting the source and drain regions, and a depletion layer formed on a part of the trench inner wall and extending from the n-type layer 6s to connect the storage electrode 7 and the n-type layer 14.
Further, in forming very small hole-shaped storage node contacts the patterning in a part of the insulator film 4 in the trench inner wall to connect the n-type layer 6s and storage node electrode 7, misalignment of masks in the patterning causes leakage problems.
As described above, in the conventional trench capacitor structures, a reduction in the S/N ratio due to the depletion layers present in the interface between the substrate and the insulator film on the trench inner wall is a problem, and it is required very strict resolution and alignment in patterning the storage node contact.